Analog isolation system with digital communication across a capacitive barrier

ABSTRACT

An isolation system is provided that is suitable for use in telephony, medical instrumentation, industrial process control and other applications. Preferred embodiments of the invention comprise a capacitive isolation barrier across which a digital signal is communicated. The system provides a means of communication across the isolation barrier that is highly immune to amplitude and phase noise interference. Clock recovery circuitry may be employed on one side of the isolation barrier to extract timing information from the digital signal communicated across the barrier, and to filter the effects of phase noise introduced at the barrier. Delta-sigma converters may be disposed on both sides of the isolation barrier to convert signals between analog and digital domains. An isolated power supply may also be provided on the isolated side of the barrier, whereby direct current is generated in response to the digital data received across the isolation barrier. Finally, a bidirectional isolation system is provided whereby bidirectional communication of digital signals is accomplished using a single pair of isolation capacitors. In preferred embodiments, the digital data communicated across the barrier consists of digital delta-sigma data signals multiplexed in time with other digital control, signaling and framing information.

TECHNICAL FIELD OF THE INVENTION

[0001] This invention relates to the field of isolation systems for usein selectively isolating electrical circuits from one another. Moreparticularly, this invention relates to isolation systems havingcapacitor-coupled isolation barriers. This invention is useful in, forexample, telephony, medical electronics and industrial process controlapplications.

BACKGROUND

[0002] Electrical isolation barriers can be identified in manyindustrial, medical and communication applications where it is necessaryto electrically isolate one section of electronic circuitry from anotherelectronic section. In this context isolation exists between twosections of electronic circuitry if a large magnitude voltage source,typically on the order of one thousand volts or more, connected betweenany two circuit nodes separated by the barrier causes less than aminimal amount of current flow, typically on the order of tenmilliamperes or less, through the voltage source. An electricalisolation barrier must exist, for example, in communication circuitrywhich connects directly to the standard two-wire public switchedtelephone network and that is powered through a standard residentialwall outlet. Specifically, in order to achieve regulatory compliancewith Federal Communications Commission Part 68, which governs electricalconnections to the telephone network in order to prevent network harm,an isolation barrier capable of withstanding 1000 volts rms at 60 Hzwith no more than 10 milliamps current flow, must exist betweencircuitry directly connected to the two wire telephone network andcircuitry directly connected to the residential wall outlet.

[0003] In many applications there exists an analog or continuous timevarying signal on one side of the isolation barrier, and the informationcontained in that signal must be communicated across the isolationbarrier. For example, common telephone network modulator/demodulator, ormodem, circuitry powered by a residential wall outlet must typicallytransfer an analog signal with bandwidth of approximately 4 kilohertzacross an isolation barrier for transmission over the two-wire, publicswitched telephone network. The isolation method and associatedcircuitry must provide this communication reliably and inexpensively. Inthis context, the transfer of information across the isolation barrieris considered reliable only if all of the following conditions apply:the isolating elements themselves do not significantly distort thesignal information, the communication is substantially insensitive to orundisturbed by voltage signals and impedances that exist between theisolated circuitry sections and, finally, the communication issubstantially insensitive to or undisturbed by noise sources in physicalproximity to the isolating elements.

[0004] High voltage isolation barriers are commonly implemented by usingmagnetic fields, electric fields, or light. The corresponding signalcommunication elements are transformers, capacitors and opto-isolators.Transformers can provide high voltage isolation between primary andsecondary windings, and also provide a high degree of rejection of lowervoltage signals that exist across the barrier, since these signalsappear as common mode in transformer isolated circuit applications. Forthese reasons, transformers have been commonly used to interface modemcircuitry to the standard, two-wire telephone network. In modemcircuitry, the signal transferred across the barrier is typically analogin nature, and signal communication across the barrier is supported inboth directions by a single transformer. However, analog signalcommunication through a transformer is subject to low frequencybandwidth limitations, as well as distortion caused by corenonlinearities. Further disadvantages of transformers are their size,weight and cost.

[0005] The distortion performance of transformer coupling can beimproved while reducing the size and weight concerns by using smallerpulse transformers to transfer a digitally encoded version of the analoginformation signal across the isolation barrier, as disclosed in U.S.Pat. No. 5,369,666, “MODEM WITH DIGITAL ISOLATION” (incorporated hereinby reference). However, two separate pulse transformers are disclosedfor bidirectional communication with this technique, resulting in a costdisadvantage. Another disadvantage of transformer coupling is thatadditional isolation elements, such as relays and opto-isolators, aretypically required to transfer control signal information, such as phoneline hookswitch control and ring detect, across the isolation barrier,further increasing the cost and size of transformer-based isolationsolutions.

[0006] Because of their lower cost, high voltage capacitors have alsobeen commonly used for signal transfer in isolation system circuitry.Typically, the baseband or low frequency analog signal to becommunicated across the isolation barrier is modulated to a higherfrequency, where the capacitive isolation elements are more conductive.The receiving circuitry on the other side of the barrier demodulates thesignal to recover the lower bandwidth signal of interest. For example,U.S. Pat. No. 5,500,895, “TELEPHONE ISOLATION DEVICE” (incorporatedherein by reference) discloses a switching modulation scheme applieddirectly to the analog information signal for transmission across acapacitive isolation barrier. Similar switching circuitry on thereceiving end of the barrier demodulates the signal to recover theanalog information. The disadvantage of this technique is that theanalog communication, although differential, is not robust. Mismatchesin the differential components allow noise signals, which cancapacitively couple into the isolation barrier, to easily corrupt boththe amplitude and timing (or phase) of the analog modulated signal,resulting in unreliable communication across the barrier. Even withperfectly matched components, noise signals can couple preferentiallyinto one side of the differential communication channel. This schemealso requires separate isolation components for control signals, such ashookswitch control and ring detect, which increase the cost andcomplexity of the solution.

[0007] The amplitude corruption concern can be eliminated by othermodulation schemes, such as U.S. Pat. No. 4,292,595, “CAPACITANCECOUPLED ISOLATION AMPLIFIER AND METHOD,” which discloses a pulse widthmodulation scheme; U.S. Pat. No. 4,835,486 “ISOLATION AMPLIFIER WITHPRECISE TIMING OF SIGNALS COUPLED ACROSS ISOLATION BARRIER,” whichdiscloses a voltage-to-frequency modulation scheme; and U.S. Pat. No.4,843,339 “ISOLATION AMPLIFIER INCLUDING PRECISION VOLTAGE-TO-DUTY CYCLECONVERTER AND LOW RIPPLE, HIGH BANDWIDTH CHARGE BALANCE DEMODULATOR,”which discloses a voltage-to-duty cycle modulation scheme. (All of theabove-referenced patents are incorporated herein by reference.) In thesemodulation schemes, the amplitude of the modulated signal carries noinformation and corruption of its value by noise does not interfere withaccurate reception. Instead, the signal information to be communicatedacross the isolation barrier is encoded into voltage transitions thatoccur at precise moments in time. Because of this required timingprecision, these modulation schemes remain analog in nature.Furthermore, since capacitively coupled noise can cause timing (orphase) errors of voltage transitions in addition to amplitude errors,these modulation schemes remain sensitive to noise interference at theisolation barrier.

[0008] Another method for communicating an analog information signalacross an isolation barrier is described in the Silicon Systems, Inc.data sheet for product number SSI73D2950. (See related U.S. Pat. Nos.5,500,894 for “TELEPHONE LINE INTERFACE WITH AC AND DC TRANSCONDUCTANCELOOPS” and 5,602,912 for “TELEPHONE HYBRID CIRCUIT”, both of which areincorporated herein by reference.) In this modem chipset, an analogsignal with information to be communicated across an isolation barrieris converted to a digital format, with the amplitude of the digitalsignal restricted to standard digital logic levels. The digital signalis transmitted across the barrier by means of two, separate high voltageisolation capacitors. One capacitor is used to transfer the digitalsignal logic levels, while a separate capacitor is used to transmit aclock or timing synchronization signal across the barrier. The clocksignal is used on the receiving side of the barrier as a timebase foranalog signal recovery, and therefore requires a timing precisionsimilar to that required by the analog modulation schemes. Consequentlyone disadvantage of this approach is that noise capacitively coupled atthe isolation barrier can cause clock signal timing errors known asjitter, which corrupts the recovered analog signal and results inunreliable communication across the isolation barrier. Reliable signalcommunication is further compromised by the sensitivity of the singleended signal transfer to voltages that exist between the isolatedcircuit sections. Further disadvantages of the method described in thisdata sheet are the extra costs and board space associated with otherrequired isolating elements, including a separate high voltage isolationcapacitor for the clock signal, another separate isolation capacitor forbidirectional communication, and opto-isolators and relays forcommunicating control information across the isolation barrier.

[0009] Opto-isolators are also commonly used for transferringinformation across a high voltage isolation barrier. Signal informationis typically quantized to two levels, corresponding to an “on” or “off”state for the light emitting diode (LED) inside the opto-isolator. U.S.Pat. No. 5,287,107 “OPTICAL ISOLATION AMPLIFIER WITH SIGMA-DELTAMODULATION” (incorporated herein by reference) discloses a delta-sigmamodulation scheme for two-level quantization of a baseband or lowfrequency signal, and subsequent communication across an isolationbarrier through opto-isolators. Decoder and analog filtering circuitsrecover the baseband signal on the receiving side of the isolationbarrier. As described, the modulation scheme encodes the signalinformation into on/off transitions of the LED at precise moments intime, thereby becoming susceptible to the same jitter (transitiontiming) sensitivity as the capacitive isolation amplifier modulationschemes.

[0010] Another example of signal transmission across an opticalisolation barrier is disclosed in U.S. Pat. No. 4,901,275 “ANALOG DATAACQUISITION APPARATUS AND METHOD PROVIDED WITH ELECTRO-OPTICALISOLATION” (incorporated herein by reference). In this disclosure, ananalog-to-digital converter, or ADC, is used to convert several,multiplexed analog channels into digital format for transmission to adigital system. Opto-isolators are used to isolate the ADC fromelectrical noise generated in the digital system. Serial datatransmission across the isolation barrier is synchronized by a clocksignal that is passed through a separate opto-isolator. The ADC timebaseor clock, however, is either generated on the analog side of the barrieror triggered by a software event on the digital side of the barrier. Ineither case, no mechanism is provided for jitter insensitivecommunication of the ADC clock, which is required for reliable signalreconstruction, across the isolation barrier. Some further disadvantagesof optical isolation are that opto-isolators are typically moreexpensive than high voltage isolation capacitors, and they areunidirectional in nature, thereby requiring a plurality ofopto-isolators to implement bidirectional communication.

[0011] Thus, there exists an unmet need for a reliable, accurate andinexpensive apparatus for effecting bidirectional communication of bothanalog signal information and control information across a high voltageisolation barrier, while avoiding the shortcomings of the prior art.

SUMMARY OF THE INVENTION

[0012] The above-referenced deficiencies in the prior art are addressedby the present invention, which provides a reliable, inexpensive,lightweight isolation system that is substantially immune to noise thataffects the timing and/or amplitude of the signal that is transmittedacross the isolating element, thus permitting an input signal to beaccurately reproduced at the output of the isolation system.

[0013] Briefly described, the invention provides a means fortransmitting and receiving a signal across a capacitive isolationbarrier. The signal is digitized and quantized to standard logic levelsfor transmission through the barrier, and is therefore largely immune toamplitude noise interference. In one embodiment of the invention, thedigital signal is synchronous and the signal is re-timed or latched onthe receiving side of the isolation barrier using a clock signal that isrecovered from the digital data sent across the barrier. The clockrecovery circuit provides a means for filtering jitter on the receiveddigital data so that the clock recovered has substantially less jitterthan the received digital signal. Consequently, the digitalcommunication across the capacitive isolation barrier is also largelyimmune to timing or phase noise interference.

[0014] In one embodiment of the present invention, the isolation barrieris comprised of two high voltage capacitors. One capacitor couples adigital voltage signal across the barrier while a second capacitorprovides a return current path across the barrier. A DC supply voltagemay be generated by an active diode bridge circuit on the receiving sideof the isolation barrier that captures energy from the transmitteddigital signal.

[0015] In an alternative embodiment of the present invention, theisolation barrier comprises two capacitors of substantially equal value,and the digital signal communicated across the barrier is a differentialsignal. A DC supply voltage may be generated by an active diode bridgecircuit on the receiving side of the isolation barrier that capturesenergy from the transmitted, differential, digital signal.

[0016] In some embodiments of the invention, the digital signal sentacross the capacitive isolation barrier is a time-division-multiplexedcombination of control or coding information and data generated by ananalog-to-digital converter (ADC) corresponding to the input analogsignal. Control information may contain, for example, signalinginformation, error detection and correction codes, and framinginformation. A decoder on the receiving side of the barrier separatesthe control information from the digital data signal. The reconstructionof the analog signal on the receiving side of the capacitive isolationbarrier is performed by a digital-to-analog converter (DAC) using aclock signal that is recovered form the digital data sent across thebarrier. In presently preferred embodiments, the ADC and DAC are singlebit, delta-sigma type converters.

[0017] In some embodiments, the invention provides a means forbidirectional communication across a capacitive isolation barrier. Inone embodiment the receiving circuit transmits digital information backto the transmitting circuit in time slots multiplexed with the timeslots used to transmit digital information from the transmitting circuitto the receiving circuit. In another embodiment, the receiving circuittransmits digital information back to the transmitting circuit in theform of a current signal quantized to levels corresponding to a digitalcurrent value. In this mode, bidirectional communication is achieved bysending a digital voltage across the barrier and, in return, sensing adigital current. The isolation barrier may be comprised of twocapacitors of substantially equal value and the bidirectional signalcommunicated across the barrier may be a differential signal. A DCsupply voltage may be generated on the receiving side of the isolationbarrier using energy captured from the transmitted signal.

[0018] The invention disclosed herein also provides a method andapparatus for enabling bidirectional communication across an isolationbarrier separating a master circuit from an isolated circuit, whereinthe master circuit includes an oscillator and a power supply, andwherein the power supply and clock signals in the isolated circuit arederived from the data signal received from the master circuit across theisolation barrier, which may be a capacitive isolation barrier.Communication from the master side to the isolated side of the barrieris as has been described above. The isolated circuit includes a clockrecovery circuit to provide an isolated clock signal that is maintainedin synchronization with the master circuit's oscillator. The isolatedclock signal and the isolated power supply circuit are then used tooperate an ADC and driver circuit on the isolated side of the barrier inorder to convert the analog signals from the isolated side to digitalsignals and to send the digital signals across the barrier to thecorresponding circuitry on the master side of the barrier, where theanalog signal is extracted. Communication in both directions(master-to-isolated and isolated-to-master) may be time multiplexed,such that there is adequate data flow from the master circuit to theisolated circuit to provide adequate energy and clock information toenable proper operation of the isolated circuit. In some embodiments ofthis invention, two capacitors of substantially equal value form theisolation barrier, and synchronous signals may be transmitted across thebarrier in both directions using a differential format.

[0019] A detailed description of preferred embodiments of this inventionis provided below, accompanied by the figures which aid in understandingthis invention.

DESCRIPTION OF THE DRAWINGS

[0020] So that the manner in which the herein described advantages andfeatures of the present invention, as well as others which will becomeapparent, are attained and can be understood in detail, more particulardescription of the invention summarized above may be had by reference tothe embodiments thereof which are illustrated in the appended drawings,which drawings form a part of this specification.

[0021] It is noted, however, that the appended drawings illustrate onlyexemplary embodiments of the invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

[0022]FIG. 1 is a block diagram of a telephone set illustrating atypical application of the present invention.

[0023]FIG. 2 is a block diagram showing a unidirectional isolationsystem according to the present invention.

[0024]FIG. 3A is a block diagram detailing the circuitry used to providea two-phase, non-overlapping clock signal to the delta-sigma modulatorsthat are used in preferred embodiments of this invention.

[0025]FIG. 3B is a timing diagram that illustrates timing relationshipsbetween various clock and data signals that occur in the circuitry ofthe present invention.

[0026]FIGS. 4A and 4B are diagrams that illustrate signal formats thatmay be produced by the encoders used in this invention.

[0027]FIG. 5 is a block diagram showing the components of exemplaryclock recovery circuit that is used in the present invention.

[0028]FIG. 6 is a schematic diagram of the active diode bridge circuitthat is used as a power supply in preferred embodiments of the presentinvention.

[0029]FIG. 7 is a block diagram illustrating a bidirectional isolationsystem according to the present invention.

[0030]FIG. 8 is a block diagram of a clock recovery and datasynchronization circuit according to a preferred embodiment of thepresent invention.

[0031]FIG. 9 is a schematic diagram of a phase detector circuit that maybe used in a clock recovery circuit according to a preferred embodimentof the present invention.

[0032]FIG. 10 is a schematic diagram of a frequency detector circuitthat may be used in a clock recovery circuit according to a preferredembodiment of the present invention.

[0033]FIG. 11 is a block diagram of a decoder circuit that may beutilized in a preferred embodiment of the present invention.

[0034]FIG. 12 is an illustration representing a framing format that maybe beneficially used in preferred embodiments of the present invention.

[0035]FIGS. 13A and 13B are schematic diagrams of driver circuits thatmay be utilized to implement the present invention.

[0036]FIG. 14 is a timing diagram illustrating an alternative framingformat that may be used in bidirectional embodiments of the presentinvention.

[0037]FIG. 15 is a block diagram of a clock recovery circuit that may beemployed for use with the framing format of FIG. 14.

DESCRIPTION OF PREFERRED EMBODIMENTS

[0038] In order to provide a context for understanding this description,FIG. 1 illustrates a typical application for the present invention: atelephone that includes circuitry powered by a source external to thephone system. A basic telephone circuit 118 is powered by the “battery”voltage that is provided by the public telephone system and does nothave a separate power connection. Many modern phones 110, however,include radio (cordless), speakerphone, or answering machine featuresthat require an external source of power 112, typically obtained byplugging the phone (or a power supply transformer/rectifier) into atypical 110-volt residential wall outlet. In order to protect publicphone system 114 (and to comply with governmental regulations), it isnecessary to isolate “powered circuitry” 116 that is externally poweredfrom “isolated circuitry” 118 that is connected to the phone lines, toprevent dangerous or destructive voltage or current levels from enteringthe phone system. (Similar considerations exist in many otherapplications as well, including communication, medical andinstrumentation applications in which this invention may be beneficiallyapplied.) The required isolation is provided by isolation barrier 120.The signal that passes through the isolation barrier 120 is an analogvoice signal in a typical telephone application, but it may also be adigital signal or a multiplexed signal with both analog and digitalcomponents in various applications. In some applications, communicationacross isolation barrier 120 may be unidirectional (in eitherdirection), but in many applications, including telephony, bidirectionalcommunication is required. Bidirectional communication may be providedusing a pair of unidirectional isolator channels, or by forming a singleisolation channel and multiplexing bidirectional signals through thechannel.

[0039] The primary requirements placed on isolation barrier 120 are thatit effectively prevents harmful levels of electrical power from passingacross it, while accurately passing the desired signal from the poweredside 122 to the isolated side 124, or in the reverse direction ifdesired.

[0040]FIG. 2 illustrates a basic block diagram of a preferred embodimentof the present invention. First the overall operation of the inventionwill be described, and then each component will be described in detailto the extent required to enable a person skilled in the art to make anduse the invention. As a matter of terminology, the circuitry shown onthe left or powered side of the isolation barrier (capacitors 209 and210 in FIG. 2) will be referred to as the “powered” circuitry or the“transmit” circuitry or system, and the circuitry on the right side ofthe isolation barrier will be referred to as the “isolated” or “receive”circuitry or system. The “transmit” side can ordinarily be identified bythe location of the dominant master oscillator 202 on that side of thebarrier, and the slave oscillator (e.g. clock recovery circuit 216) islocated on the receive side. Note, however, that in some embodiments ofthe present invention signals may be transmitted from the receive systemto the transmit system, so these terms do not necessarily indicate thedirection of data flow across the barrier. Furthermore, in someembodiments the master oscillator may be on the low-power (e.g.telephone system) side of the barrier, and a clock recovery PLL may belocated on the high-power side of the barrier.

[0041] Referring to FIG. 2, a preferred unidirectional capacitiveisolation system according to the present invention includes adelta-sigma analog to digital converter 201 operable on the analog input212 and driven by a clock signal from oscillator 202. The digital outputof the delta-sigma ADC 224 is synchronous with the operating frequencyof oscillator 202 and time division multiplexed with digital controlsignals 219 by encoder circuit 213. The encoder circuit 213 also formatsthe resulting digital data stream 230 into a coding scheme or framingformat that allows for robust clock recovery on the receiving side ofthe isolation barrier. The isolation barrier comprises two high voltagecapacitors 209 and 210. In one embodiment of the present invention,driver circuit 214 drives the transmit side of capacitor 209 with adigital voltage signal. Clock recovery circuit 216 presents a very highimpedance to the receive side of capacitor 209, allowing the digitalvoltage output of driver 214 to couple across the isolation barrier. Inthis embodiment, capacitor 210 provides a return current path across thebarrier. In another embodiment, capacitors 209, 210 are differentiallydriven by complementary digital outputs of driver circuit 214. In thatembodiment, clock recovery circuit 216 presents a very high impedance tothe receive sides of capacitors 209 and 210, allowing the differentialdigital voltage outputs of driver 214 to couple across the isolationbarrier. The input to driver circuit 214 is the output 230 of encoder213.

[0042] The receive side of the isolation barrier includes clock recoverycircuit 216, with inputs connected to isolation capacitors 209 and 210.The clock recovery circuit recovers a clock signal from the digital datadriven across the isolation barrier. The recovered clock providesclocking signals for decoder 217 and delta-sigma digital-to-analogconverter 208. Decoder circuit 217 separates the time divisionmultiplexed data signal from control signals, providing a digitalcontrol output 228 and data output 232 that is routed to delta-sigma DAC208. The delta-sigma DAC 208, with digital input supplied from decoder217 and clock supplied from clock recovery circuit 216, provides theanalog output of the receive side of the isolation system, which closelycorresponds to the original analog input 212.

[0043] Active diode bridge circuit 640 may also be connected toisolation capacitors 209 and 210 to provide a DC voltage source 220 toclock recovery circuit 216 and decoder circuit 217 derived from energycontained in the signal transmitted across the isolation barrier.

[0044] In the descriptions of preferred embodiments that follow, allcircuit references are made with respect to MOS (metaloxide-semiconductor) integrated circuit technology, although theinvention may be implemented in other technologies as well, as will beunderstood by one skilled in the art. A preferred embodimentincorporates transmit system 225 consisting of delta-sigma ADC 201,oscillator 202, encoder 213 and driver 214 fabricated on one siliconsubstrate, and receive system 226 consisting of clock recovery circuit216, decoder 217, delta-sigma DAC 208 and active diode bridge 640fabricated on a second silicon substrate. The two separate siliconsubstrates are required to maintain the high voltage isolation providedby capacitors 209 and 210, since typical MOS technologies cannot providehigh voltage isolation of 1000 volts or greater.

[0045] The delta-sigma analog-to-digital converter, shown as block 201of FIG. 2, is well known in the art. See, for example, J. C. Candy, AUse of Double Integration in Sigma Delta Modulation, IEEE Trans. OnCommunication, March 1985, pp. 249-258, and B. E. Boser and B. A.Wooley, The Design of Sigma-Delta Modulation Analog-to-DigitalConverters, IEEE Journal Solid State Circuits, December 1988, pp.1298-1308, both of which are incorporated herein by reference. Thespecific design of ADC 201 will be a matter of design choice dependingupon the needs of the particular application in which the isolationbarrier will be used.

[0046] The use of a delta-sigma converter within the isolation systemprovides several desirable features. It will be appreciated that thedelta-sigma converter uses a high oversampling rate to provide accurateA/D conversion over the input signal bandwidth without the use ofprecisely matched components or high-order, analog anti-aliasingfilters. Moreover, such converters occupy a relatively small amount ofspace on an integrated circuit and are relatively easy to fabricate on aCMOS chip.

[0047] The digital pulse stream 224 output from delta-sigma converter201 encodes the analog input signal 212 in a pulse density modulationformat. In pulse density modulation, the amplitude information of theanalog input signal is contained in the density of output pulsesgenerated during a given interval of time.

[0048] Suitable designs for oscillator circuit 202 are well known in theart and may typically comprise a ring oscillator, relaxation oscillator,or an oscillator based on a piezo-electric crystal disposed external tothe integrated MOS circuit. See, for example, A. B. Grebene, Bipolar andMOS Analog Integrated Circuit Design, John Wiley and Sons, 1984, whichis incorporated herein by reference. FIG. 3A further illustrates theclock signals that may be provided to delta-sigma converter 201 in apreferred embodiment of this invention. Clock signal 302 from oscillator202 is input to clock divider circuit 304 that divides the frequency ofthe input clock and provides an output in the form of two phase,non-overlapping clock signals Ø₁ and Ø₂ to the delta-sigma modulatorcircuit. The design and construction of clock divider circuit 304 iswithin the ordinary skill in the art and is not detailed here. Sinceencoder circuit 213 may perform time-division multiplexing of thedigitized data signal 224 with digital control input data 219 using atime base derived from oscillator 202, clock divider 304 of FIG. 3A musttypically divide the frequency of oscillator 202 by at least a factor oftwo.

[0049]FIG. 3B illustrates exemplary signals associated with clockdivider circuit 304 and delta-sigma modulator 201 in FIG. 3A. Trace 310is the clock signal received from oscillator 202 on line 302. Trace 312is the “clock divided by 2” signal that is generated by clock dividercircuit 304. Traces 314 and 316 illustrate exemplary two phase,non-overlapping clock signals Ø₁ and Ø₂, respectively, that may beoutput from clock divider circuit 304 to delta-sigma modulator 201.Trace 318 represents the analog input to ADC 201, which generallychanges very slowly in comparison to the frequency of clock signal 310.This bandwidth relationship is required because the delta-sigmamodulator must operate at a sampling rate much higher than a typicalNyquist rate (for example, a 1 MHz sampling rate for a 4 kHz voicebandsignal is typical) in order for the information in the analog signal tobe accurately represented by the single-bit binary output. Finally,trace 320 represents the digital output of delta-sigma modulator 201,which may, for example, be synchronized to the rising edge of clocksignal Ø₁. (The illustrated output bit pattern 320 is provided to showexemplary timing relationships and does not attempt to accuratelyreflect the illustrated analog input 318).

[0050] Referring to FIG. 2, the encoder circuit 213 performs two primaryfunctions in preferred embodiments of this invention. The first functionof encoder 213 is time-division multiplexing of control signals 219 fromother circuitry and data signals 224 from the delta-sigma modulator 201,an operation that is well known in the art and subject to many suitableimplementations. The multiplexing function is synchronized by clocksignals from oscillator 202. The second function of encoder 213 isformatting the data for transmission across isolation capacitors 209,210. FIG. 4 details one coding scheme that may be used to transmitdigital pulses across the capacitive isolation barrier. (Anothersuitable coding scheme is described below with reference to FIG. 14.)FIG. 4A shows the format for data sent from the transmit circuit to thereceive circuit. When data=1 for a given bit cell, the output of theencoder is high for the first quarter of the bit cell period. Whendata=0 for a given bit cell, the output of the encoder is high for thethird quarter of the bit cell period. This coding scheme guarantees onelow-to-high transition followed by one high-to-low transition for everybit cell period, independent of the data pattern. The resulting dataindependent transition density allows for robust clock recovery in thereceiving circuitry on the other side of isolation capacitors 209, 210.Alternatively, robust clock recovery can also be achieved by use of apreamble used for frequency locking followed by a data pattern which isnot of constant average frequency.

[0051] In a bidirectional system, as is described below in connectionwith FIG. 7, the transmit system encoder 702 and driver 703 maycooperate to provide a high-impedance tri-state output to the isolationcapacitor 705 during either the last half of the bit cell period 410 (iftransmit data=1) or the first half of the bit cell period 411 (iftransmit data=0) as shown in FIG. 4a. This permits transmission ofinformation from the receive system to the transmit system during thatportion of each bit cell when the transmit driver 703 is tri-stated.

[0052] In a preferred embodiment, at the beginning of each bit cellperiod the receive system decoder section 708 detects whether thetransmit circuit has sent a data=1 pulse across the isolation barrier.If a transmit data=1 pulse was sent, the receive driver remainstri-stated until the second half of the bit cell period, during whichtime a receive data=0 or 1 pulse can be sent back across the isolationbarrier to the transmit system. If a transmit data=1 pulse is notdetected by the receive circuit the receive driver sends receive data=0or 1 during the first half of the bit cell period and tri-states for thesecond half of the bit cell period. This operation is shown in FIG. 4B.

[0053] In those embodiments in which the digital, bidirectionalcommunication is differential, capacitors 705 and 706 are driven bycomplementary digital voltages in both directions, and the drivercircuits associated with both capacitors are tri-stated during selectedportions of the bit cell period in accordance with the coding schemeshown in FIG. 4.

[0054] A preferred embodiment of the unidirectional driver circuit 214of FIG. 2 is detailed in FIG. 13A for single ended (not differential)communication and FIG. 13B for differential communication across thecapacitive isolation barrier. Referring to FIG. 13A, the transmitcircuit driver 214 may comprise an inverter 250 driven by the encoderoutput signal 230. The output of inverter 250 drives the transmitcircuit side of isolation capacitor 209 to transmit logic levels definedby the transmit V_(DD) and ground voltage levels. The clock recoveryinput buffer presents a high impedance to the receive side of capacitor209, thereby allowing the receive side of capacitor 209 to attainsubstantially the same logic levels as the transmit side of capacitor209. In this manner the digital logic signal is effectively coupledacross the capacitive isolation barrier.

[0055] Capacitor 210 is disposed between the transmit circuit groundnode 254 and receive circuit ground node 256 in order to form a groundcurrent return path across the isolation barrier. This path is requiredbecause the clock recovery buffer input impedance, although high, is notinfinite. Therefore a small current must flow across the barrier andback in order to couple the digital logic signal across the barrier.Furthermore, capacitor 209 must deliver charge to the active diodecircuit 640 (FIG. 2) in order that a supply voltage for several receivecircuit sections can be provided. The current associated with thistransfer of charge from the transmit circuit to the receive circuit musthave a path to return to the transmit circuit.

[0056] The single-ended communication system described above isinsensitive to voltage signals that may exist between the transmitcircuit ground 254 and receive circuit ground 256 provided that the rateof change of such voltage signals is substantially less than thefrequency of the digital signal transmitted across the barrier. Thesingle-ended method is also insensitive to resistive and capacitiveimpedances that may exist between the transmit circuit ground 254 andreceive circuit ground 256. The system can be desensitized to inductiveimpedances that may exist between the transmit circuit ground 254 andreceive circuit ground 256 by adding resistive elements in series withcapacitor 210, in series with the transmit ground connection 254, inseries with the receive ground connection 256, or any combination ofthese.

[0057]FIG. 13B shows an example of a suitable differential driver 258for unidirectional digital communication across a capacitive isolationbarrier. The inverter 260 that drives capacitor 209 is driven by thedigital signal output from the transmit encoder circuit 213, whileinverter 261, which drives capacitor 210, is driven by the complement231 of the digital signal output from transmit encoder circuit 213.Clock recovery input buffer 262 presents high impedances to the receivesides of capacitors 209 and 210, allowing the differential digitaltransmit voltages to couple across the isolation barrier. In thisdifferential communication method, both capacitors 209 and 210 providereturn current paths across the isolation barrier. The differentialdigital communication system described above is largely insensitive tovoltage signals and impedances that may exist between the transmitcircuit ground 254 and receive circuit ground 256, since these voltagesand impedances appear as common mode influences in differentialcommunication.

[0058] Bidirectional communication across the barrier can be supportedby additional driver and receive buffer structures, similar to thoseshown in FIG. 13, without the need for any additional isolationelements, providing that inverters 250, 260, 261, which drive the highvoltage isolation capacitors, can be tri-stated generally in accordancewith the timing diagram shown in FIG. 4 or any other suitable coding andtiming scheme. In some embodiments, additional capacitor drivinginverters that can be tri-stated may be provided in a receive-sidedriver circuit 713 (FIG. 7) and input buffers may be provided in atransmit side decoder circuit 714.

[0059] In presently preferred embodiments, the actual isolation barriercomprises a pair of isolation capacitors 209 and 210, which are highvoltage capacitors that may be chosen for a particular application toprevent DC and low frequency current flow across the barrier and protectthe isolated circuitry from high voltage faults and transients, whilepermitting data at selected transmission frequencies to cross thebarrier. The capacitors must be capable of withstanding anticipatedvoltages that may appear due to faults in the powered circuitry 225, inorder to provide the protective function that is the purpose of thebarrier. For example, in preferred embodiments ordinary 2000 voltcapacitors with capacitance on the order of 100 pF may be utilized inthe isolation barrier. In a barrier system in accordance with thepresent invention it is not necessary to use high precision capacitors,because the system is very tolerant of variations in capacitorperformance due to environmental influences, such as variations involtage and temperature.

[0060] A preferred embodiment for a clock recovery circuit 216 for usein this invention is detailed in FIG. 5 and described below. One sectionof the clock recovery circuit may be a phase locked loop (“PLL”)circuit, consisting of phase/frequency detector 531, charge pump 532,resistor 533, capacitor 534, and voltage controlled oscillator (“VCO”)535. The other section of the clock recovery block is data latch 542operating outside the phase locked loop to re-time the digital datareceived across the isolation barrier. Circuitry for performing thesefunctions is well known to those skilled in the art. See, for example,F. Gardner, Phaselock Techniques, 2d ed., John Wiley & Sons, New York,1979; and R. Best, Phase-Locked Loops, McGraw-Hill, 1984, which areincorporated herein by reference. The data input to the receive systemfrom the isolation capacitors may be derived from a differential signalpresent at the barrier by passing the differential signal through MOSinput buffers (not shown), which are well known in the art, andproviding a single-ended binary output signal 530 to the clock recoverycircuit.

[0061] The illustrated exemplary phase/frequency detector 531 receives adigital input 530 from the isolation barrier and an input 536 from theoutput of VCO 535 and performs a phase comparison between these twoinputs. If the VCO phase lags the input data phase, a speed up signal538 is supplied to charge pump 532. If the input data 530 phase lags theVCO output 536 phase, a slow down signal 540 is supplied to charge pump532. In response to “speed up” inputs from phase/frequency detector 531,charge pump 532 delivers a positive current to the loop filterconsisting of resistor 533 and capacitor 534 connected in series. Inresponse to “slow down” inputs from the phase/frequency detector, chargepump 532 sinks a positive current from the loop filter. The outputvoltage of the loop filter at node 542 drives voltage controlledoscillator 535, which increases its operation frequency as the inputvoltage increases. The output of VCO 535 is fed back as input 536 tophase/frequency detector 531, and it is also used to re-time the inputdata 530 by serving as the clock input to flip-flop latch 542, thusproviding a clock signal to the isolated circuitry and also providingdata signal 546 that is synchronized to clock signal 544. A dividercircuit may be included in the feedback path 536.

[0062] The phase/frequency detector and charge pump operate to increaseloop filter voltage 542 and VCO frequency if VCO phase 536 lags inputdata phase 530. Conversely, the VCO frequency is decreased if the VCOphase leads input data phase. In this manner, the VCO output phase isadjusted until phase lock is achieved with input data. Consequently, theVCO frequency is driven to be substantially identical to the input datafrequency.

[0063] If noise interference occurs at the isolation barrier, the inputdata transitions will occur at points in time that are noisy, orjittered, relative to the transition times of the transmit circuitdriver. These jittered data edges will cause a noise component in thecharge pump current that drives the loop filter. The loop filter andVCO, however, low-pass filter this noise component, substantiallyattenuating the effects of this input data jitter. Consequently, the VCOoutput signal, while frequency locked to the input data, containssubstantially less phase noise than the noisy input data. The bandwidthof the phase noise filtering operation may be set independently of thebandwidth of the analog signal to be communicated across the isolationbarrier. Since the filtered, phase locked loop output clock signal 544is used to latch or re-time the noisy input data at flip flop 542, theeffects of noise interference at the capacitive isolation barrier aresubstantially eliminated. Finally, the filtered, phase locked loopoutput clock signal 544 is used as the timebase or clock for the otherreceive circuits, including decoder 217 and delta-sigma DAC 208 shown inFIG. 2, resulting in an analog output 218 of the capacitive isolationsystem that is substantially free from any noise interference that mayhave been introduced at the capacitive isolation barrier.

[0064] Preferred embodiments of active diode bridge circuit 640 of FIG.2 are detailed in FIG. 6A for single-ended digital communication andFIG. 6B for differential digital communication across the isolationbarrier. The active diode bridge generates a DC power supply voltageV_(DD), which may be used to operate the clock recovery and receiverdecoder circuits, in response to the digital data received across thecapacitive isolation barrier. An active diode bridge circuit isdistinguished from a standard or passive diode bridge in that the gatingelements are active transistors rather than passive elements such asbipolar diodes.

[0065] Referring to the exemplary circuit illustrated in FIG. 6A,isolation capacitor 209 is connected to node 625 and isolation capacitor210 is connected to node 626. The source of n-channel MOSFET 621 and thesource of p-channel MOSFET 622 are connected to node 625. Also connectedto node 625 is the input of standard CMOS inverter 623. The output ofinverter 623 drives the gates of MOSFETS 621 and 622. The drain ofn-channel MOSFET 621 is connected to node 626, the receive circuitground node, while the drain of p-channel MOSFET 622 connects to node627, which provides V_(DD) voltage for the isolated circuitry. Alsoconnected to V_(DD) node 627 are load capacitor CL 624 and the powersupply input of CMOS inverter 623. In a preferred embodiment, the powersupply inputs of clock recovery circuit 216 and decoder circuit 217shown in FIG. 2 are also connected to V_(DD) node 627.

[0066] Referring to the exemplary embodiment illustrated in FIG. 6A, theoperation of the active diode bridge circuit used in single-endeddigital communication will now be described. A digital logic signal iscoupled across capacitor 209 from the transmit section. When a digital“high” signal is received through capacitor 209, node 625 goes high. Thelogic “high” signal on node 625 forces the CMOS inverter 623 output nodeto go low, turning off device 621 and turning on device 622.Consequently, current flows through capacitor 209, device 622, and fromV_(DD) to receive circuit ground through capacitor CL and through clockrecovery and decoder circuitry shown in FIG. 2. The circuit is completedby current flow returning across the isolation barrier through capacitor210. The current demand by circuitry on V_(DD) through capacitors 209and 210 must be limited so that the voltage on node 625 relative to node626 can still be recognized as a digital high logic level. When adigital “low” signal is received through capacitor 209, CMOS inverter623 turns off device 622 and turns on device 621. Consequently, currentflows across the isolation barrier through capacitor 210, through device621, and returns across the isolation barrier through capacitor 209.Therefore, although no average current flows through capacitors 209 and210, average current can be supplied from V_(DD) to receive circuitground to operate clock recovery circuit 216 and decoder circuit 217.Load capacitor 624 operates to minimize supply ripple on the DC supplyvoltage established on node V_(DD).

[0067] Referring to the embodiment shown in FIG. 6B, isolation capacitor209 connects to node 646 and isolation capacitor 210 connects to node647. The source node of n-channel MOSFET 641 and the source node ofp-channel MOSFET 642 connect to node 646. Also connected to node 646 arethe gates of n-channel MOSFET 643 and p-channel MOSFET 644. The sourcenode of n-channel MOSFET 643 and the source node of p-channel MOSFET 644connect to node 647. Also connected to node 647 are the gates ofn-channel MOSFET 641 and p-channel MOSFET 642. The drains of devices 641and 643 are connected to the ground node of the receiving circuit. Thedrains of devices 642 and 644 are connected to the node 220, whichprovides V_(DD) voltage for the isolated circuitry. Also connected toV_(DD) node 220 are load capacitor C_(L) 645 and the power supply inputsof clock recovery circuit 216 and decoder circuit 217 as shown in FIG.2.

[0068] Referring to the exemplary embodiment illustrated in FIG. 6B, theoperation of the active diode bridge used in differential digitalcommunication will now be described. A differential digital signal isreceived through capacitors 209 and 210. When a digital ‘high’ signal isreceived through capacitor 209, a corresponding digital ‘low’ signal isreceived through capacitor 210, and node 646 goes high while node 647goes low. This condition turns on devices 642 and 643 while turning offdevices 641 and 644. Consequently, current flows through capacitor 209,device 642, from V_(DD) to ground through capacitor C_(L) and throughclock recovery circuitry 216 and decoder circuitry 217 shown in FIG. 2.The circuit is completed from receive circuit ground 650, through device643 and finally returning across the isolation barrier through capacitor210. The current demand on V_(DD) must be limited so that the voltage onnode 646 relative to node 650 can be recognized as a high logic levelsignal by the clock recovery and decoder circuitry.

[0069] When a digital ‘low’ signal is received through capacitor 209, adigital ‘high’ signal is received through capacitor 210, and node 646goes low while node 647 goes high. This condition turns on devices 641and 644 while turning off devices 642 and 643. Consequently currentflows through capacitor 210 and device 644 to V_(DD) node 220, and fromthere to ground through capacitor 645 and through clock recovery anddecoder circuitry shown in FIG. 2. The circuit is completed from ground650, through device 641 and finally returning across the isolationbarrier through capacitor 209. Therefore, in either logic state, andindependently of the current flow direction through capacitors 209 and210, current flows in the same direction from V_(DD) to ground.Therefore, an average or DC supply voltage is established on nodeV_(DD), and adequate current can be supplied to operate clock recoverycircuit 216 and decoder circuit 217. Load capacitor 645 operates tominimize power supply ripple, providing a filtering operation on V_(DD).An added benefit of the ability to power sections of the isolatedcircuitry from the digital signal transmitted across the capacitiveisolation barrier from the powered circuitry is that it allows isolatedpower-up and power-down control of isolated circuitry sections on anas-needed basis.

[0070] Parasitic bipolar transistors may result from typical CMOSprocesses. If they are not controlled, these bipolar transistors candischarge the power supply 627 shown in FIG. 6A during the initial powerup time. If the discharge current from the parasitic bipolar transistorsis larger than the current delivered to the power supply 627 throughtransistor 622, then the circuit may not power up to the desired fullvoltage level. The beta of a lateral bipolar transistor in any CMOSprocess is a function of layout. With appropriate layout (i.e., largebase region), the beta can be kept small enough to minimize undesireddischarge currents. Further care needs to be taken in the design of anycircuit that is connected to power supply 627. The circuits connected topower supply 627 cannot draw more current from the power supply than isavailable from the active diode bridge, even before the supply hasramped to the full value. Circuit design techniques to address theseissues are common and well known in the art.

[0071] In the illustrative embodiment shown in FIG. 2, delta-sigmadigital to analog converter (DAC) 208 receives input data from decoder217 and synchronous clock input from clock recovery circuit 216. Analogoutput signal 218 is generated by DAC 208 in response to the digitaldata that is communicated across the capacitive isolation barrier. Theoutput signal 218 is highly immune to amplitude and phase noise that maybe introduced in the barrier circuitry because the signal that iscommunicated across the isolation capacitors is a synchronous digitalsignal, and because the received data is resynchronized to therecovered, jitter-filtered clock signal. The DAC is also timed by thatclock signal. Delta-sigma DAC technology is well known in the art, andselecting a suitable DAC circuit will be a matter of routine designchoice directed to the intended application of the barrier circuit. See,for example, P. Naus et al., A CMOS Stereo 16-Bit D/A Converter forDigital Audio, IEEE Journal of Solid State Circuits, June 1987, pp.390-395, which is incorporated herein by reference.

[0072]FIG. 7 illustrates a preferred bidirectional embodiment of thepresent invention. It will be recognized that other unidirectional andbidirectional isolation barriers may be designed by persons skilled inthe art using the principles described herein, and that such barrierswill fall within the scope of this invention. In the illustrated anddescribed embodiment, the capacitive isolation system comprises a“transmit” system to the left of center, a “receive” system to the rightof center, and a capacitive isolation barrier in the center of thefigure comprising two high voltage capacitors 705 and 706. Note that theterms “transmit” and “receive” are used to identify the powered andisolated sides of the barrier, respectively, and that in this embodimentdata may be conveyed across the barrier in both directions. Many of thecomponents in this bidirectional embodiment are identical or similar tothose in the unidirectional embodiment described above with reference toFIG. 2.

[0073] The transmit system includes delta-sigma analog-to-digitalconverter 701 operable on the analog input 720 of the transmit circuitand synchronized to clock signal 722 from oscillator 704. The analoginput 720 of the transmit system is an analog signal containinginformation to be transmitted across the isolation barrier, which may befor example an analog voice signal to be coupled to a telephone system.Digital output 724 of the delta-sigma ADC may be time-divisionmultiplexed with digital control input 726 by the encoder circuit 702.Digital control input 726 is a digital signal containing additionalinformation to be transmitted across isolation barrier 705, 706. Digitalcontrol input 726 may include control information for analog circuitryon the receiving side of the isolation barrier. Encoder circuit 702 alsoformats the resulting data stream into a coding scheme that allows forrobust clock recovery on the receiving side of the isolation barrier, asis described above.

[0074] Encoder circuit 702 also receives a clock signal 722 fromoscillator 704. Driver circuit 703 of the transmit system drives theencoded signal to isolation capacitors 705 and 706 in response to theoutput of encoder circuit 702.

[0075] The isolation barrier comprises two high voltage capacitors 705,706. In one embodiment, capacitor 705 is driven bidirectionally bydrivers 703, 713 while capacitor 706 provides a return path across theisolation barrier. In another embodiment of the present invention,capacitors 705 and 706 are differentially driven by digital drivercircuits 703, 713.

[0076] A preferred embodiment of the receive system, shown to the rightof isolation capacitors 705, 706 in FIG. 7 includes clock recoverycircuit 707, whose inputs are connected to isolation capacitors 705,706. The clock recovery circuit recovers a clock signal from the digitaldata driven across the isolation barrier and provides synchronized clocksignal 730 to the various circuits in the receive system. The recoveredclock operates as the time base for decoder 708 and delta-sigmadigital-to-analog converter 709. Decoder section 708 separates the timedivision multiplexed data and control information, providing digitalcontrol output 732 to other circuitry, and providing synchronous datasignal 734 as an input to delta-sigma DAC 709. The delta-sigma DAC 709,with digital input 734 supplied by decoder 708, and clock signal 730supplied by clock recovery section 707, operates synchronously with thetransmit system delta-sigma ADC 701 and provides analog output 736 onthe receiving side of the isolation barrier. Active diode bridge 710 isconnected to isolation capacitors 705 and 706 and supplies a DC powersupply voltage to clock recovery circuit 707 and decoder circuit 708 bydrawing current from the digital signal transmitted across the isolationbarrier, as is described in detail above. Driver 713 must remaintri-stated until decoder 708 has detected a valid frame, indicatingsuccessful power-up of the receive circuit sections.

[0077] The embodiment shown in FIG. 7 also enables communication fromthe receive system to the transmit system, or from right to left acrossthe isolation capacitors as illustrated. The receive system encodercircuit 712 and driver circuit 713 cooperate to communicate informationback from the receive system to the decoder circuit 714 in the transmitsystem. Receive system encoder section 712 receives a clock input 730from clock recovery section 707, and is thereby synchronized to thetransmit system oscillator 704 and encoder 702. This synchronizationallows transmission in each direction to occur in distinct time slots.In time slots where transmit driver 703 is operable to transmitinformation from the transmit system to the receive system, receivedriver 713 is tri-stated or disabled. Alternatively, in time slots wherereceive driver 713 is operable to transmit information back from thereceive system to the transmit system, transmit driver 703 is tri-statedor disabled. In this manner, bidirectional communication may beestablished across a single pair of high voltage isolation capacitors.

[0078] Digital control input 738 of the receive system is a digitalsignal containing information to be communicated across the isolationbarrier, including control information for analog circuitry on thetransmit system side of the barrier. The receive system also includesdelta-sigma ADC 711 operable on analog input signal 740 so that theinformation contained in analog signal 740 on the receive system side ofthe isolation barrier can be conveyed across the barrier in digital formand then accurately reproduced on the transmit system side of thebarrier. The receive system delta-sigma ADC 711 receives its clock inputfrom clock recovery circuit 707, and is thereby synchronized withtransmit system oscillator 704. Digital output signal 742 generated byreceive system ADC 711 may be time-division multiplexed with receivesystem digital control input 738 in encoder section 712.

[0079] In the transmit system, decoder circuit 714 is connected toisolation capacitors 705, 706 to receive signals therefrom, identifysignals representing information coming from the receive system. Decoder714 then extracts the digital control information from the data streamreceived from the receive circuit, and passes data signal 744 generatedby delta-sigma ADC 711 to transmit system delta-sigma DAC 715. Decoder714 also latches and retimes the data received across the barrier tosynchronize it with clock signal 722, which is generated by oscillator704, thereby eliminating the effects of phase noise interference andother sources of jitter in the synchronous digital signal. Circuits thatare suitable for performing these decoder functions are well known inthe art.

[0080] Transmit system delta-sigma DAC 715 receives its clock input fromoscillator 704 and is thereby synchronized to receive system ADC 711.Transmit system DAC 715 provides a reconstructed analog data outputsignal 746, thereby completing the communication of analog informationback from the receive system to the transmit system.

[0081] In summary, FIG. 7 describes a bidirectional communication systemfor conveying analog and digital information across a capacitiveisolation barrier. The barrier itself is inexpensive, since only twohigh voltage isolation capacitors are required for synchronous,bidirectional communication. The barrier is a reliable communicationchannel because the digital signals communicated across the barrier areinsensitive to amplitude and phase noise interference that may beintroduced at the isolation barrier.

[0082] A more detailed description of a clock recovery circuit suitablefor use in this invention with the coding scheme of FIG. 4 will now beprovided, with reference to FIG. 8. Clock recovery PLL 805 has datainput 530, data output 546 and recovered clock signal output 544. Phasedetector 810 has inputs DATA 530 and feedback clock signal CK2 545. Theoutputs of phase detector 810 are SPEED-UP1 and SLOW-DOWN1 signals, bothof which are connected to inputs of phase detector charge pump 816.Frequency detector 818 has inputs DATA 530 and output clock signal CK4544. The outputs of frequency detector 818 are signals designatedSPEED-UP2 and SLOW-DOWN2, which are connected to the inputs of frequencydetector charge pump 824. The outputs of phase detector charge pump 816and frequency detector charge pump 824 are connected together and arealso connected to the input of voltage controlled oscillator (“VCO”) 535and one terminal of resistor 533. The other terminal of resistor 533 isconnected to one terminal of capacitor 534. The other terminal ofcapacitor 534 is connected to ground. The output of VCO 535 is the CK2signal 545. The clock input of flip-flop 826 is connected to CK2 545.The Q-bar output of flip-flop 826 is connected to the D input offlip-flop 826. The Q and Q-bar outputs of flip-flop 826 are connected tothe inputs of multiplexer (mux) 828. The control input 830 of mux 828 iscalled MUX CONTROL and comes from the framing logic, which is describedelsewhere in this specification. The output of mux 828 is the CK4 signal544. The D input of flip-flop 542 is connected to data input 530. Theclock input of flip-flop 542 is connected to the CK4 signal 544. The Qoutput of flip-flop 542 is the resynchronized DATAOUT signal 546, whichis sent to the frame detect logic.

[0083] Frequency detector 818 is dominant over phase detector 810 whenthe frequency of the DATA and CK4 signals are different. Once thefrequency of the DATA and CK4 signals are substantially similar, theSPEED-UP2 and SLOW-DOWN2 signals become inactive and phase detector 810becomes dominant. Separate charge pumps for the phase detector andfrequency detector allow for independent control of the gain of thephase detector and frequency detector circuits. Alternatively, ifindependent gains are not required, then the SPEED-UP1 and SPEED-UP2signals could be logically ORed together to drive one charge pump. Andlikewise the SLOW-DOWN1 and SLOW-DOWN2 signals could be logically ORedtogether to drive the other input to the charge pump.

[0084] The output of VCO 535 is the CK2 signal, which is divided by twoin frequency by flip-flop 826. Since CK2 is divided by two to generatethe bit rate clock signal CK4, there can be two phases of CK4 withrespect to the start of a bit period. The phase of CK4 that will yieldcorrect operation of the frequency detector is the one where the risingedge of CK4 aligns with the start of a bit period. The frame-detectlogic is needed to detect the start of a bit interval and is used toselect the appropriate phase of CK4 using mux 828.

[0085] It will be appreciated that a clock recovery circuit according tothis invention, such as that illustrated in FIG. 8 or FIG. 15, may bebeneficially used to recover and stabilize a clock signal on theisolated side of the barrier where the clock signal is conveyed viaisolation elements that are separate from the isolation elements thatare used to transfer the data signal.

[0086] A preferred embodiment of a decoder circuit 708 is shown in FIG.11. Shift register 840 has an input connected to the DATAOUT signal 546from clock recovery circuit 805 and is clocked by recovered clock signalCK4. Multi-bit output 842 of shift register 840 is connected toframe-detect logic 844 and to demux logic 846. Frame detect logic 844has one output connected to mux control logic 848 and one outputconnected to demux logic 846. Demux logic 846 is clocked by CK4. Counter850 is also clocked by CK4. The output of counter 850 is connected tomux control logic 848. The output of mux control logic 848 is theMUX-CONTROL signal 830 sent to the clock recovery PLL 805 to select theproper phase for the CK4 signal. The outputs of demux logic 846 are theDEMUXED DATA signal and the CONTROL signal.

[0087] Shift register 840 stores a predetermined number of bits of theserial DATAOUT signal 546. Frame-detect logic 844 operates on this dataand detects when a frame signal is received. Many possible framingsignal formats can be used. A format that may be used in a presentlypreferred embodiment is shown in FIG. 12. Data 860 is alternated withframing signals 862 and control signals. In the framing format shown inthis figure, one control signal (off hook) 864 is sent for every eightdata bits. The remaining seven bits in the frame of sixteen are used forframe synchronization. The illustrated framing signal is six onesfollowed by a zero in the control signal field. The data signal may beguaranteed to not have more than five ones in a row so that it will notbe mistaken for a framing signal. Many other framing formats arepossible to allow for different data signal properties and to permit theuse of additional control bits.

[0088] Once the frame detect logic 844 detects six one's followed by azero in the control signal field, mux control logic 848 is set tomaintain the phase of the CK4 signal. If after a predetermined number ofCK4 clock cycles a framing signal is not detected, then counter 850 willcause mux control logic 848 to change the phase of CK4 using mux 828(FIG. 8). Counter 850 will then be reset, and frame detect logic 844will again attempt to detect the selected framing signal so as toachieve synchronization. Only the correct phase of CK4 will achieveframe synchronization. Once frame synchronization is achieved, demuxlogic 846 can correctly decode control and data signals.

[0089] The specific structure and operation of frame detect logic 844,demux logic 846, and mux control logic 848 is dependent upon theselected framing format, the selected multiplexing scheme, and otherdesign choices. The detailed design of this circuitry is within theordinary skill in the art and is omitted from this description of apreferred embodiment.

[0090] Exemplary embodiments of phase and frequency detectors 810, 818are shown in FIGS. 9 and 10. Referring to FIG. 9, phase detector 810 hasinput signals CK2 and DATA and output signals SPEED-UP1 and SLOW-DOWN1.A two input NAND gate 860 has inputs DATA and CK2 and its output isconnected to one input of NAND gate 862. A two input NOR gate 864 alsohas inputs DATA and CK2 and its output is connected to the input ofinverter 866. A two input NAND gate 868 has one input connected to theoutput of the inverter 866 and one input connected to the output of NANDgate 862. NAND gate 862 has one input that is connected to the output ofNAND gate 860 and the other input connected to the output of NAND gate868. A three input AND gate 870 has one input connected to the output ofinverter 872, another input connected to the DATA signal and anotherinput connected to the output of NAND gate 862. The output of AND gate870 is the SLOW-DOWN1 signal. The input of inverter 872 is connected tothe CK2 signal. A three input AND gate 874 has one input connected tothe output of NAND gate 862, another input is connected to the CK2signal and another input is connected to the output of inverter 876. Theoutput of AND gate 874 is the SPEED-UP1 signal. The input of inverter876 is connected to receive the DATA signal.

[0091] In the illustrated embodiment, phase detector 810 compares thephase on the falling edges of DATA and CK2 after both signals are highat the same time. NAND gates 862 and 868 form a set-reset type latch.The latch gets “set” such that the output of NAND gate 862 is high whenboth the DATA and CK2 signals are high. The latch gets “reset” such thatthe output of NAND gate 862 is low when both DATA and CK2 are low. Whenthe latch is “set” (i.e., both DATA and CK2 are high), AND gates 870 and874 are enabled. Once the AND gates 870 and 874 are enabled they cancompare the falling edges of CK2 and DATA to determine which signal goeslow first. If DATA goes low first, then the SPEED-UP1 signal will gohigh until CK2 also goes low, indicating that oscillator 535 needs tooscillate faster in order to achieve phase alignment with the DATAsignal. If the CK2 signal goes low first then the SLOW-DOWN1 signal willgo high until DATA also goes low, indicating that oscillator 535 shouldoscillate slower in order to achieve phase alignment with the DATAsignal. The SPEED-UP1 and SLOW-DOWN1 signals are connected to phasedetector charge-pump 816.

[0092] A preferred embodiment of frequency detector 818 is shown in FIG.10. The inputs to frequency detector 818 are the DATA and CK4 signalsand the outputs are the SPEED-UP2 and SLOW-DOWN2 signals. Delay cell 880has its input connected to CK4 and output connected to one input of NORgate 882. The delay cell 880 consists of an even number of capacitivelyloaded inverter stages or other delay generating circuitry and is wellknown in the art. The output of inverter 884 is connected to the otherinput of NOR gate 882 and the input of inverter 884 is connected to CK4.The output 886 of NOR gate 882 is reset pulse that occurs on the risingedge of CK4, and is connected to the reset input of D flip-flops 888,890, and 892. The input of inverter 894 is connected to DATA. The outputof inverter 894 is connected to the clock input of D flip-flops 888,890, and 892. The D input of flip-flop 888 is connected to V_(DD). TheD-input of flip-flop 890 is connected to the Q-output of flip-flop 888.The D-input of flip-flop 892 is connected to the Q-output of flip-flop890. D flip-flops 894 and 896 have their clock inputs connected to CK4.The D input of flip-flop 894 is connected to the Q output of flip-flop888. The D-input of flip-flop 896 is connected to the Q-output offlip-flop 890. The input of inverter 898 is connected to the Q-output offlip-flop 894, and the output of inverter 898 is the SLOW-DOWN2 signal.OR gate 900 provides the SPEED-UP2 signal. One input of OR gate 900 isconnected to the Q-output of flip-flop 896, and the other input isconnected to the Q-output of flip-flop 892. The SPEED-UP2 and SLOW-DOWN2signals are connected to the frequency-detector charge pump 824.

[0093] The illustrated embodiment of frequency detector 818 counts thenumber of DATA pulses within one CK4 cycle. The frequency of CK4 shouldequal to the bit rate of the DATA pattern. Suitable encoding used forthe DATA signal will ensure that there will be only one CK4 rising edgefor each data pulse falling edge, if the frequency of CK4 is equal tothe data rate. If the CK4 frequency is equal to the data rate then theQ-output of flip-flop 888 will be high prior to each rising edge of CK4and the Q-outputs of flip-flops 890 and 892 will be low prior to eachrising edge of CK4. If the Q-output of flip-flop 888 is low prior to therising edge of CK4 then the SLOW-DOWN2 signal will go high for theduration of the next CK4 cycle, signaling that oscillator 535 shouldslow down. If the Q-output of flip-flop 890 is high prior to the risingedge of CK4, then the SPEED-UP2 signal will go high for the duration ofthe next CK4 cycle signaling that the oscillator should speed up.

[0094] Another exemplary data coding scheme that may be used in anisolation system constructed in accordance with this invention is shownin FIG. 14. In this scheme, each bit period 570 is split into fourfields. The first field 572 is referred to as the clock field and isalways high independent of the data being transferred. The second field574, which may occupy the second quarter of the bit period 570, containsthe forward-going (from transmit side to receive side) data bit. Thisdata bit can be either the delta-sigma data bit or a control bit or anydesired type of encoding bit, in accordance with the requirements of theapplication in which the invention is used. The third field 576, whichmay occupy the third quarter of the bit period, is always low to ensureenough signal transitions to provide for power transmission in theforward path along with the first two fields, at least one of which ishigh in each bit period. The forward (transmit side) driver circuit istri-stated during the fourth field 578, thus allowing for datatransmission in the opposite direction across the isolation capacitor.Of course, this particular coding scheme is provided as an example, andmany other coding schemes may be devised that will be operable in thevarious embodiments of the present invention.

[0095] It is desirable to use the logic “1” that is present at thebeginning of each bit period for clock recovery, since it is alwayspresent at periodic intervals. However, if the reverse data bit from theprevious bit period is a one, the rising edge at the beginning of thenext bit period will not be readily seen by a logic gate and thereforewill not be useful for clock recovery. To mitigate this effect and toallow reliable clock recovery, every fourth bit in the reverse field maybe guaranteed to be zero by the encoding algorithms that are employed.The total frame length can be increased if more control bits need to besent across the barrier in the reverse direction. Every fourth clockedge (the one associated with a zero in the previous reverse bit field )may then be used for clock recovery.

[0096] A block diagram of an exemplary PLL circuit that can performclock recovery in accordance with the coding scheme of FIG. 14 is shownin FIG. 15. The forward data (conveyed from the transmit side to thereceive side) is connected to divide-by-four counter 800. The output ofcounter 800 is connected to phase-frequency detector 801. The output ofphase-frequency detector 801 is connected to charge pump 802. The outputof charge pump 802 is connected to the input of loop filter 803. Theoutput of loop filter 803 is connected to the input of voltagecontrolled oscillator (VCO) 804. The output of VCO 804 is the bit clockused for synchronizing the received data signal and for providing aclock signal to the receive side circuitry. The output of VCO 804 isalso connected to the input of divide-by-four counter 805. The output ofcounter 805 is connected to the other input of phase-frequency detector801. The phase-frequency detector 801 and the other circuits in theillustrated clock recovery circuit of FIG. 15 are well known in the art,and the specific circuitry selected for a particular application wouldbe a matter of routine design choice.

[0097] Further modifications and alternative embodiments of thisinvention will be apparent to those skilled in the art in view of thisdescription. Accordingly, this description is to be construed asillustrative only and is for the purpose of teaching those skilled inthe art the manner of carrying out the invention. It is to be understoodthat the forms of the invention herein shown and described are to betaken as the presently preferred embodiments. Various changes may bemade in the shape, size and arrangement of parts. For example,equivalent elements may be substituted for those illustrated anddescribed herein, and certain features of the invention may be utilizedindependently of the use of other features, all as would be apparent toone skilled in the art after having the benefit of this description ofthe invention.

We claim:
 1. An isolation barrier for conveying an electrical signalfrom a transmitting circuit to a receiving circuit while electricallyisolating the transmitting circuit from the receiving circuit,comprising: an isolation capacitor; a synchronous analog-to-digitalconverter having an input connected to the transmitting circuit forreceiving the electrical signal to be transmitted across the barrier,and an output connected to a first side of the isolation capacitor forproviding a synchronous digital signal to the isolation capacitor; asynchronous digital-to-analog converter having an input connected to asecond side of the isolation capacitor for receiving the synchronousdigital signal therefrom, and having an output connected to thereceiving circuit for providing an analog signal thereto.
 2. Theisolation barrier of claim 1, wherein the barrier comprises a pair ofisolation capacitors, and wherein the synchronous digital signal is adifferential signal.
 3. The isolation barrier of claim 1, furthercomprising a power supply having an input connected to the second sideof the isolation capacitor to receive the synchronous digital signaltherefrom, the power supply comprising a rectifier circuit for providinga DC voltage derived from energy contained in the synchronous digitalsignal.
 4. A telephone set comprising the isolation barrier of claim 1.5. A modem comprising the isolation barrier of claim
 1. 6. The isolationbarrier of claim 1, wherein the synchronous analog-to-digital convertercomprises a delta-sigma modulator and wherein the synchronousdigital-to-analog converter comprises a delta-sigma modulator.
 7. Anisolation barrier for conveying an analog data signal from atransmitting circuit to a receiving circuit while electrically isolatingthe transmitting circuit from the receiving circuit, comprising: a) ananalog-to-digital converter having an input connected to receive theanalog data signal from the transmitting circuit and an output providinga synchronous digital data signal; b) an encoder circuit connected tothe output of the analog-to-digital converter for encoding the digitaldata signal into a selected format; c) an oscillator circuit connectedto the analog-to-digital converter and to the encoder circuit to providea clock signal thereto; d) a driver circuit connected to receive theencoded digital signal from the encoder circuit and providing a digitaloutput signal; e) a first isolation capacitor having an input connectedto receive the digital output signal from the driver circuit; f) a clockrecovery circuit having an input connected to an output of the isolationcapacitor, the clock recovery circuit providing a clock signal that issubstantially synchronized with the clock signal provided by theoscillator circuit; g) a decoder circuit having a decoder inputconnected to the isolation capacitor output, a clock input connected toreceive a clock signal from the clock recovery circuit, and a digitaldata output; and h) a digital-to-analog converter connected to thedigital data output, the digital-to-analog converter having an outputterminal for providing an isolated analog signal to the receivingcircuit.
 8. The isolation system of claim 7, wherein theanalog-to-digital converter and the digital-to-analog converter comprisedelta-sigma modulators.
 9. The isolation system of claim 7, furthercomprising a second isolation capacitor having an input and an output,and wherein the driver circuit is a differential output driver circuithaving differential outputs connected to the inputs of each of the firstand the second isolation capacitors, and wherein the clock recoverycircuit has differential inputs connected to the outputs of each of thefirst and the second isolation capacitors.
 10. The isolation system ofclaim 7, further comprising an isolated DC power supply circuit havingan input connected to the first isolation capacitor and a power supplyoutput connected to the clock recovery circuit and to the decodercircuit, the power supply circuit comprising a rectifier circuit and afilter circuit.
 11. The isolation system of claim 7, wherein the encodercircuit comprises a digital control signal input for receiving a digitalcontrol signal from the transmitting circuit, and a multiplexer formultiplexing the digital control signal with the digital data signal,and wherein the decoder circuit comprises a demultiplexer for separatingthe digital control signal from the digital data signal.
 12. A methodfor conveying an analog signal from a transmitting circuit to areceiving circuit while electrically isolating the transmitting circuitfrom the receiving circuit, comprising: converting the analog signal toa synchronous digital signal; transferring the synchronous digitalsignal across a capacitive isolation barrier to provide an isolateddigital signal; converting the isolated digital signal to an analogoutput signal.
 13. The method of claim 12, further comprising recoveringa clock signal on the receiving circuit side of the barrier, andsynchronizing the isolated digital signal to the recovered clock signal.14. The method of claim 12, wherein the converting steps include usingdelta-sigma modulation.
 15. The method of claim 12, further comprisingrectifying part of the isolated digital signal on the receiving side ofthe barrier to provide a DC power supply.
 16. A bidirectional isolationbarrier for conveying analog data signals between a powered circuit andan isolated circuit while electrically isolating the powered circuitfrom the isolated circuit, the barrier comprising: a first isolationcapacitor; a powered-side signal processing system including: a firstsynchronous analog-to-digital converter having an input connected to thepowered circuit for receiving an analog data signal to be transmittedacross the barrier in a first direction, and an output connected to afirst side of the isolation capacitor for providing a synchronousdigital signal to the isolation capacitor; a first synchronousdigital-to-analog converter having an input connected to said first sideof the isolation capacitor for receiving synchronous digital signalstherefrom when data signals are transmitted in a second direction fromthe isolated circuit to the powered circuit, and having an outputconnected to the powered circuit for providing analog signals thereto;an isolated-side signal processing system including: a secondsynchronous digital-to-analog converter having an input connected to asecond side of the isolation capacitor for receiving a synchronousdigital signal therefrom when the data signals are transmitted in saidfirst direction, and having an output connected to the isolated circuitfor providing a reconstructed analog data signal thereto; and a secondsynchronous analog-to-digital converter having an input connected to theisolated circuit for receiving an analog data signal to be transmittedacross the barrier in said second direction to the powered circuit, andan output connected to the second side of the isolation capacitor forconveying a synchronous digital signal corresponding to said analog datasignal to the isolation capacitor.
 17. The isolation barrier of claim16, further comprising a second isolation capacitor, and wherein thesynchronous digital signal passed across the first and second capacitorsis a differential signal.
 18. The isolation barrier of claim 16, theisolated-side signal processing system further comprising a power supplycircuit having an input connected to the first isolation capacitor toreceive the synchronous digital signal, the power supply comprising arectifier circuit for providing a DC voltage signal.
 19. A telephone setcomprising the isolation barrier of claim
 16. 20. The isolation barrierof claim 16, wherein the synchronous analog-to-digital converterscomprise delta-sigma modulators and wherein the synchronousdigital-to-analog converters comprise delta-sigma modulators.
 21. Theisolation barrier of claim 16, further comprising a clock recoverycircuit having an input connected to the isolation capacitor forreceiving the synchronous digital signal therefrom, the clock recoverycircuit having a data output and a clock output, the clock outputproviding a recovered clock signal, and the data output providing adigital data signal that is synchronized with the recovered clocksignal.
 22. The isolation barrier of claim 21, wherein the clockrecovery circuit comprises a phase locked loop circuit including afilter circuit to reduce jitter in the recovered clock signal.
 23. Anisolated digital-to-analog converter for converting synchronous digitalsignals received from an isolation barrier into analog signals,comprising: a clock recovery circuit having an input connected to theisolation barrier and being adapted to produce a recovered clock signalthat is synchronized to the synchronous digital signals, the clockrecovery circuit comprising a latch for resynchronizing the synchronousdigital signals to the recovered clock signal; and a synchronousdigital-to-analog converter having a clock input connected to receivethe recovered clock signal from the clock recovery circuit, a data inputconnected to receive the resynchronized digital signals from the clockrecovery circuit, and an analog output.
 24. The isolateddigital-to-analog converter of claim 23, wherein the synchronousdigital-to-analog converter comprises a delta-sigma modulator.
 25. Theisolated digital-to-analog converter of claim 23, wherein the clockrecovery circuit comprises a phase locked loop and a filter circuit. 26.A method for transmitting an analog data signal across a capacitiveisolation barrier, comprising: converting the analog signal to a digitaldata signal; combining the digital data signal with control informationto form a digital encoded signal; driving the digital encoded signalacross the capacitive isolation barrier; receiving an isolated encodedsignal from the isolation barrier; recovering a clock signal from theisolated encoded signal; synchronizing the isolated encoded signal withthe clock signal; separating the isolated encoded signal into anisolated digital data signal and isolated control information; andconverting the isolated digital data signal into an isolated analogsignal.
 27. The method of claim 26, wherein the converting steps includeusing delta-sigma modulation to perform the analog to digital conversionand the digital to analog conversion.
 28. An isolation system forproviding a digital communication channel between a powered circuit andan isolated circuit, the isolation system comprising an isolationbarrier and a clock recovery circuit located on an isolated side of theisolation barrier, the clock recovery circuit adapted to provide arecovered clock signal based on isolated signals received from thepowered circuit across the isolation barrier, the recovered clock signalbeing substantially free of phase noise, the isolation system furthercomprising an analog to digital converter having an input connected tothe powered circuit and an output connected to the isolation barrier,and a digital to analog converter having an input connected to theisolation barrier and an output connected to the isolated circuit. 29.The isolation system of claim 28, wherein the isolation barriercomprises one or more capacitors.
 30. The isolation system of claim 28,wherein the digital communication channel is bidirectional.
 31. Theisolation system of claim 28, wherein the clock recovery circuitcomprises a phase-locked loop circuit.
 32. The isolation system of claim31, wherein the phase-locked loop circuit comprises a loop filtercircuit for reducing the effects of phase noise on the recovered clocksignal.
 33. The isolation system of claim 28, wherein the isolatedsignals are data signals.
 34. The isolation system of claim 28, whereinthe isolated signals are clock signals.
 35. The isolation system ofclaim 28, wherein the analog to digital converter and the digital toanalog converter are delta sigma converters.
 36. A bidirectionalisolation system for providing an isolated communication channel fordata signals in a forward direction and in a reverse direction across anisolation barrier comprised of isolation elements, the systemcomprising: a powered system on a first side of the isolation barrier,the powered system comprising a powered analog to digital converterhaving a data input terminal and an output connected to a first drivercircuit, the first driver circuit being connected to the isolationbarrier for driving a forward direction digital signal across theisolation barrier; and an isolated system on a second side of theisolation barrier, the isolated system comprising an isolated analog todigital converter having a data input terminal and an output connectedto a second driver circuit, the second driver circuit being connected tothe isolation barrier for driving a reverse direction digital signalacross the isolation barrier; wherein the forward direction digitalsignal and the reverse direction digital signal are both driven throughthe same isolation elements.
 37. The isolation system of claim 36,wherein the isolation elements are capacitors.
 38. The isolation systemof claim 36, wherein the first and second driver circuits aredifferential driver circuits.
 39. The isolation system of claim 36,wherein the forward direction digital signal comprises said data signalmultiplexed with a control signal.
 40. The isolation system of claim 36,wherein the forward direction digital signal comprises said data signalmultiplexed with a control signal.
 41. The isolation system of claim 36,wherein the analog to digital converters are delta sigma converters. 42.An isolation system for providing a digital communication channel fordata signals and control signals, the isolation system comprising: anisolation barrier; an analog to digital converter connected to receivethe data signals having an output for providing digitized data signals;a multiplexer located on one side of the isolation barrier and connectedto receive the digitized data signals and the control signals andproviding a multiplexed digital signal that is connected to theisolation barrier; a demultiplexer located on the other side of theisolation barrier and connected to receive the multiplexed digitalsignal from the isolation barrier, the demultiplexer having a digitizeddata signal output and a control signal output; and a digital to analogconverter having an input connected to the digitized data signal outputand an analog output terminal.
 43. The system of claim 42, wherein theisolation barrier is a capacitive isolation barrier.
 44. The system ofclaim 42, wherein the multiplexed digital signal is conveyed across theisolation barrier as a differential digital signal.
 45. The isolationsystem of claim 42, wherein the analog to digital converter and thedigital to analog converter are delta sigma converters.